CLKDIV=0000, VSBIAS=0000, VREFSEL=0, SDADLPM=0
Startup Control Register 1
| CLKDIV | SDADC24 reference clock division select 0 (others): Settings are prohibited. 0 (0000): SDADCCLK (no division) 1 (0001): SDADCCLK/2 (1/2) 2 (0010): SDADCCLK/3 (1/3) 3 (0011): SDADCCLK/4 (1/4) 4 (0100): SDADCCLK/5 (1/5) 5 (0101): SDADCCLK/6 (1/6) 6 (0110): SDADCCLK/8 (1/8) 7 (0111): SDADCCLK/12 (1/12) 8 (1000): SDADCCLK/16 (1/16). |
| Reserved | These bits are read as 000. The write value should be 000. |
| SDADLPM | A/D conversion operation mode select 0 (0): Normal A/D conversion mode: SDADC24 reference clock:4 MHz, Oversampling clock:1 MHz 1 (1): Low-power A/D conversion mode(1/8 of the clock in normal A/D conversion mode): SDADC24 reference clock:500 kHz,Oversampling clock: 125 kHz |
| VSBIAS | Reference voltage select 0 (others): Settings are prohibited. 0 (0000): 0.8 V 1 (0001): 1.0 V 2 (0010): 1.2 V 3 (0011): 1.4 V 4 (0100): 1.6 V 5 (0101): 1.8 V 6 (0110): 2.0 V 7 (0111): 2.2 V 15 (1111): 2.4 V (This voltage can be set only if VREFSEL = 1. When VREFSEL = 0, 2.2 V is set (rather than 2.4 V)) |
| Reserved | These bits are read as 000. The write value should be 000. |
| VREFSEL | VREF mode select 0 (0): Internal VREF mode 1 (1): External VREF mode |